Hardware and Secure Implementation of Enhanced ZUC Steam Cipher Based on Chaotic Dynamic S-Box

Volume 10, Issue 1, Page No 37-47, 2025

Author’s Name: Mahdi Madani ¹, El-Bay Bourennane ¹, Safwan El Assad ²

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¹ Laboratoire ImViA (EA 7535), Université Bourgogne Europe, 21000 Dijon, France
² IETR, University of Nantes/Polytech Nantes, France

^a)whom correspondence should be addressed. E-mail: Mahdi.Madani@u-bourgogne.fr

Adv. Sci. Technol. Eng. Syst. J. 10(1), 37-47 (2025); DOI: 10.25046/aj100105

Keywords: Dynamic S-box, FPGA design, Hardware metrics, ZUC stream cipher, Mobile security, Cryptography, Cryptanalysis

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Abstract

Despite the development of the Internet and wired networks such as fiber optics, mobile networks remain the most used thanks to the mobility they offer to the user. However, data protection in these networks is more complex because of the radio channels they use for transmission. Hence,there is a need to find more sophisticated data protection means to face any attack. But, this is not an easy task, especially with the emergence of AI-based attacks. In this context, we proposed in this work a solution that can significantly improve data protection in a new-generation mobile network. Therefore, the main objective of this study is to improve and implement an enhanced version of the standard ZUC algorithm designed by the Data Assurance and Communication Security Research Center of the Chinese Academy of Sciences and standardized by the 3GPP (3rd Generation Partnership Project) organization to ensure the LTE (Long Term Evolution of radio networks) security. The proposed design is principally based on replacing the static Sboxes of the original algorithm (S 0 and S 1) with a chaos-based dynamic S-boxes thus allowing to generate a different key stream for any change on the secret key and with the best randomness and robustness properties. The two new dynamic S-boxes are initialized with 256 initialization values each (x”00”), then filled in parallel using two chaotic maps that use the ZUC algorithm registers, the CK (Cipher Key), and the IV (Initial Vector) to form two different initial values for each chaotic map. To reach the hardware performance, we implemented the system on a Xilinx XC7Z020 PYNQ-Z2 FPGA platform. The designed architecture occupies low logic resources (1135 Slice LUTs, 762 Slice Registers, and 8 DSP48E1) on the used FPGA device and can reach a throughput of 2515.84 Mbps with a running frequency of 78.62 Mhz by consuming only 0.188 W. To evaluate the resistance of the proposed cryptosystem, we used many security tests (keystream distribution, keystream randomness, key sensitivity, plaintext sensitivity, keyspace, and NIST statistical tests). The experimental results and comparison with other S-boxes based algorithms prove on one hand that using the dynamic S-box technique has enforced considerable data protection against cryptanalysis attacks, and on another that the hardware metrics (used logic resources, achieved throughput, and efficiency) are suitable for real-time applications such as mobile security transmission.

Received: 14 October 2024 Revised: 05 January 2025 Accepted: 06 January 2025 Online: 04 February 2025

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Hardware and Secure Implementation of Enhanced ZUC Steam Cipher Based on Chaotic Dynamic S-Box