1. Introduction

Portable and wearable/implantable devices are gaining worldwide acceptance among consumer/biomedical electronics. Circuit de- signs in such devices have a bottleneck on power dissipation and chip area. Log-domain circuits are one of the best possibilities in ex- ploring low power, high dynamic range analog designs. Log-domain filters and transconductance-capacitor (G_m C) filters can be used in biological data acquisition system which involves low frequency signals like ECG (electrocardiogram) and EEG (electroencephalo- gram). Since the transistors in these log-domain filters are working in sub-threshold mode of operation (weak-inversion), a low cutoff frequency can be achieved with low values of bias currents (order of nA). This paper is an extension of work originally presented in [1].

The cutoff frequency ( f_o) of log-domain and G_m     C filters is given by (1) [2, 3].  where k, T and q have their usual meanings.

Equation (1) shows the direct relation between cutoff frequency and bias current. I_o is usually generated from a current reference circuit. The current reference should be stable against variations in process and supply voltage. Supply voltage sensitivity is the parameter which shows the stability of the current reference against supply voltage variations. Lower supply voltage sensitivity indicates a better current reference. Depending on the mode of operation of transistors in the circuit or the topology of the filter architecture, the current reference can be a temperature independent or Propor- tional to Absolute Temperature (PTAT) current reference. From (1) and (2), in log-domain and G_m    C filters, it is evident that f_o has an inverse relationship with temperature. To fix this problem, I_o is generated in such a way that it has also a linear relationship with temperature. Thus a PTAT current reference is used to bias log-domain/G_m − C filters. As a cumulative effect, the filter cutoff

where η, I_o and V_T are sub-threshold slope factor, bias current and thermal voltage respectively. Equation (2) gives the expression for thermal voltage.

frequency remains constant over temperature variations.

Many PTAT current reference designs are explored in the lit- erature. Beta-multiplier based circuits discussed in [4]–[5] have adequate PTAT current characteristics. However, to generate low reference currents under low supply voltage for low frequency fil- ters used in biological data acquisition system, larger values of

resistors are needed which occupies large area on chip. Moreover the control over temperature coefficient of resistance also becomes difficult. A comprehensive research has been carried out on the   region), (3) can be approximated to (4). conventional PTAT designs to tackle such shortcomings [6]–[7]. In [7], self-cascode transistors are used instead of resistor. This improves supply variation rejection, but linearity in current versus temperature characteristic has been compromised. In [8], compos- ite transistors are used in the PTAT circuit to enhance the supply voltage sensitivity, but large resistor values are needed to generate smaller currents. In [2, 9], switched capacitors are used in place of resistor. But PTAT current is generated from PTAT voltage us- ing opamp circuits like voltage to current converter which in turn increases the overall power dissipation of the circuit. [1] shows a good switched capacitor based PTAT reference. But the settling time of the reference current is compromised.

Settling time of current reference becomes a significant aspect especially in high speed applications. When the settling time of the reference current increases, the circuit which uses this reference current to generate its bias current also takes a significant amount of time to settle its bias current to steady state value. In case of a filter used in a wireless communication system, it takes a significant time to fix its cutoff frequency which may lead to attenuation of relevant

signal information. For example, the circuit presented in [1] requires 8 ms to stabilise its current which means that it takes around 8 ms for the subsequent filter to fix its cutoff frequency which is biased by this reference current source. This work proposes a feasible solution

Figure 1: Beta-multiplier circuit

From Figure 1, the reference current I_{re f} which is also the drain current of M₂ (I_D2) can be written as (5). to this problem.

In this paper, a fast settling PTAT current source is proposed.

A startup circuit added to the PTAT source improves the settling time of reference current. The proposed circuit exhibits good PTAT characteristics and better stability against power supply fluctuations. This can be used to bias low frequency filters in biomedical appli- cations. A low power log-domain filter is also designed and biased using the proposed PTAT current source. Results show that the cutoff frequency of the filter remains constant irrespective of tem- perature variations. This paper is organized as follows. Details of the proposed PTAT circuit along with the results are given in Section

2. Log-domain filter realisation and filter response are detailed in Section 3. Finally conclusions are drawn in Section 4.

2. Proposed Improved PTAT Reference

When transistor operates in weak-inversion region, its drain Voltage across resistor R (V_R) can be given as (6).A conventional beta-multiplier based current source circuit [5] is shown in Figure 1. Depending on the mode of operation of transis- tors, it can be a constant-G_m biasing circuit [5] or a PTAT current source. It acts as former if all the transistors work in strong-inversion saturation region (V_GS > V_th and V_DS     V_GS     V_th) and as latter if all the transistors work in weak-inversion saturation (V_GS < V_th and V_DS ≥ 3V_T ).

Using (4), gate-source voltages of M₁ and M₂ can be expressed as (7) and (8) respectively.

V_th2j can be written as (9) [11] to include the body effect of  By substituting (7) and (8) in (6) and by assuming V_th1 = V_th2, V_R can be derived as following.

Thus, I_{re f} can be expressed as (11). current [10] can be expressed as following.

Assuming R is thermally stable, I_{re f} is directly proportional to

where I_D0 = µ_nC_ox(η  1)V_T ²; µ_n and C_ox are electron mobility and gate oxide capacitance per unit area respectively. Other terms have their usual meanings. For V_DS ≥ 3V_T (weak-inversion saturation temperature thereby giving PTAT characteristics. For lower val- ues of currents (order of nAs), large values of resistors are needed. For example, to generate a reference current of 1 nA using circuit shown in Figure 1, a 10 MΩ resistor is required if p is chosen as 1.5. To accommodate such large resistors on chip, huge area is needed which makes the circuit more process dependent, hence reducing the accuracy of I_{re f} . In a typical SoC (System-on-Chip), where digital circuits and analog circuits co-exist together, a stable and precise clock will be available. In such systems, the resistor R in Figure 1 can be replaced by a switched capacitor driven by this clock which significantly enhances accuracy of I_{re f} . Improved PTAT current reference

Figure 2: Block diagram

The entire block diagram of the circuit setup explained in this paper is shown in Figure 2. The startup circuit is added to the PTAT current generator to reduce the settling time of I_{re f} thereby improving the transient response.

By substituting R_eq (12) in place of R in (11), we get (13).

From (13) it can be seen that, I_{re f} is directly proportional to C₁.

If f_clk and p are chosen properly, smaller capacitor values can be obtained for the currents in the order of nA.

Figure 4: Error amplifier

The purpose of error amplifier which is shown in Figure 4 is to make the drain voltages of M₁ and M₂ equal thereby making currents through them equal. This kind of biasing minimises the de- pendency of I_{re f} on V_DD which improves supply voltage sensitivity. It takes around 8 ms for the reference current to settle to the steady state value of 1 nA in the circuit presented in [1]. To reduce this delay, a startup arrangement comprising of M₁₀, M₁₁ and C_S is added to the circuit. A similar kind of startup circuit is discussed in [12]. In Figure 3, when the circuit is switched on and before it reaches the steady state, initially the gates of M_1,2 and M_3,4 are at zero volt and V_DD respectively. Assuming zero initial voltage across

Figure 3: Proposed improved PTAT current reference

The transistor level implementation of PTAT current reference along with startup arrangement is shown in Figure 3.  In the pro-

the capacitor C_S , M₁₀ turns on and pulls up the gates of M_1,2 to V_DD. M_1,2 start conducting and I_{re f} rises. Then, potential at the gates of M_3,4 drops and M₁₁ turns on. C_S starts to charge towards V_DD and potential at the gate of M₁₀ increases and once the circuit reaches steady state, M₁₀ turns off. M₁₀ and M₁₁ do not have a static current path from V_DD to ground. Hence startup circuit dissipates zero static power.

Value of capacitor C_S and sizes of M₁₀ and M₁₁ determine how fast startup circuit can initialise the main circuitry and how fast it can be disconnected once main circuitry reaches the steady state. Transistors M₁₀ and M₁₁ operate in linear region and the linear on resistance of these transistors are given by (14).

posed circuit, every transistor is working in weak-inversion region. The value of p is chosen as 1.5 which means that the size of M₂ is 1.5 times the size of M₁. A switched capacitor comprising of capacitor C₁ and transmission gate switches (M_n and M_p) is used in place of resistor. M_p is selected 4 times larger than M_n in the transmission gate so that its on resistance does not depend on the voltage across it. Two clocks (‘clk’ and ‘clk’) which are complementary to each other and having frequency f_clk are used for the switching operation. When ‘clk’ becomes high (‘clk’ becomes low), capacitor C₁ charges and when ‘clk’ becomes low (‘clk’ becomes high), it discharges. The average resistance (R_eq) of the switched capacitor is given as in (12) [5].

How fast startup circuit is switched on depends on how fast transistor M₁₀ turns on. The on time of M₁₀ is limited by the input capacitance of M₁₀ which comprises of gate to source and gate to drain capacitances. By properly choosing the size of M₁₀, the on time can be optimised.

When it comes to disconnection of startup circuitry, assuming M₁₁ as a linear resistance given by (14), the RC time constant (τ) of the branch consisting of M₁₁ and C_S is given by (15).

When capacitor C_S charges above the voltage (V_DD V_th), M₁₀ turns off. (V_DD   V_th) is approximately 150 mV in this design and time for C_S to charge to this voltage (30 % of final value) from 0.5 V supply through M₁₁ is nearly 0.4τ.

A low pass filter which comprises of R and C₂ is added to main- tain the ripple content in the output reference current within the accepted level. Capacitor C₂ is chosen as 0.1 pF and resistor R is tuned to obtain the ripple content in I_{re f} less than 1 %. To remove high frequency noise during switching operation, capacitor C_A is used at the source of M₂. A 100 kHz clock is selected for this work. The capacitors, C₁, C_A, C_S are taken as 0.8 pF, 10 pF, 1 pF respectively. By substituting (13) in (1), f_o can be expressed as (16).

From (16), it can be seen that f_o is independent of temperature.

2.1   Simulation results

The proposed circuit is designed using UMC 65 nm CMOS process with a supply voltage of 0.5 V. Periodic Steady State (PSS) analysis is carried out to plot the reference current. Figure 5 shows the out- put current generated (1 nA) for one clock period (10 µs) at room

Figure 7: I_{re f} for different supply voltages

Figure 8: I_{re f} across the process corners

Figure 5: I_{re f} at V_DD= 0.5 V

Figure 6 shows I_{re f} variations when temperature is varied from linearly with temperature and thus has a good PTAT characteristics over the range of temperature.

Figure 9: Transient response of the current flowing through M₂

Figure 10: Transient response of the current flowing through M₅

I_{re f} is plotted for different values of V_DD at room temperature as shown in Figure 7. I_{re f} is 0.996 nA and 1.018 nA for V_DD of 0.4 V and 0.9 V respectively. The supply voltage sensitivity of I_{re f} is found to be 3.23 %/V by considering these extreme values.

Figure 8 plots I_{re f} for various process corners at room tempera- ture and V_DD = 0.5 V. I_{re f} deviates maximum in ss and ff corners (1.034 nA and 0.968 nA). The maximum deviation is less than 3.6

The current flowing through the source of M₂ is shown in Figure

9. It has ripples having peak to peak magnitude of approximately

where I_in contains both dc current I_dc and input current I_signal. I_K is the current flowing through M₃ which contains both capacitor current I_C and I_dc.   I_out is the output current. Equation (19) can be realized using a translinear loop having four transistors. These equations can be implemented in the form of a translinear circuit as shown in Figure 11 [15]. 0.1 nA. The ripple free current flowing through M₅ is shown in Figure 10. The settling time is found to be approximately 1 ms.

Table 1: Comparison of the proposed work with other similar works

[7] [13] [14] [1] This work Technology (nm) 1500 180 40 65 65 Supply voltage (V) 1.2 1.2 1 0.5 0.5 Reference current (nA) 0.4 6 100 1 1 Settling time (ms) – – – 8 1 Power (nW) 2 – 350 1.5 1.5 Supply voltage sensitivity (%/V) 6 6.47 2.9 2.7 3.2

The improved PTAT reference consumes a power of 1.5 nW at room temperature from a supply voltage of 0.5 V. The proposed circuit along with existing PTAT current references in the literature are listed in Table 1 and a fair comparison is done. The proposed

Figure 11: First order log-domain filter

In this circuit, the MOSFETs M₁–M₄ form the translinear loop. These transistors are working in sub threshold saturation region. The cutoff frequency of the filter can be tuned by varying the DC current and is given by following [16].

PTAT circuit functions under the lowest supply voltage and has a very low supply voltage sensitivity and settles faster than [1] (nearly 87 % improvement in settling time).

3. Log-Domain Filter Realization

The proposed PTAT current source shows excellent PTAT character- istics. To verify this, a low frequency log-domain filter is designed and biased with the proposed switched capacitor based PTAT cur- rent reference. This log-domain filter can be used in low power biomedical applications like processing of ECG, EEG signals. The expectation is that the cutoff frequency of the filter remains the same irrespective of the variations in temperature.

The transfer function of a first order low-pass filter is The ideal DC current sources shown in Figure 11 can be re- placed by current sources implemented using MOSFETs. In this work I_dc is taken as I_{re f} (1 nA). The cutoff frequency of 100 Hz is obtained by choosing C=37 pF. time domain differential equation is given by

where x(t) and y(t) represent the input and output currents of the filter respectively. By solving the differential equations and relating the current-voltage in transistor operating in subthreshold operation, we get

Figure 12: AC response of the filter biased with temperature independent current reference

3.1    Simulation results

The filter is designed using UMC 65 nm CMOS technology with a supply voltage of 0.5 V. For a comparison, I_dc is generated from a temperature independent current reference and ac response of the filter is plotted. Figure 12 shows the variation of cutoff frequency in the temperatures ranging from 10^◦C to 80^◦C. The maximum deviation is found to be 16 %. To verify the PTAT characteristics, I_dc is generated from the proposed PTAT source and ac response is plotted. Figure 13 shows that deviation of cutoff frequency is negligible and maximum deviation is found to be less than 2 %. The band transitions are enlarged in corresponding inset graphs. Table 2 shows the deviation of filter cutoff frequency for both temperature independent and the proposed PTAT references.

Figure 13: AC response of the filter biased with PTAT current reference

Table 2: Cutoff frequency deviation

Temperature (◦C)	Cutoff frequency (Hz)
	Temp. independent	PTAT
-10	116	101.9
0	107	101.2
27	100	100
50	93	99
80	88	98.4

Table 3 lists the parameters of the filter designed in this work.

Table 3: Parameters of the filter

Technology	65 nm CMOS
Supply voltage	0.5 V
Power	2.5 nW
Cutoff frequency	100 Hz
DC gain (at 27◦C )	0.94
Iin pp at 25 Hz for 1% THD	0.82 nA
Input referred noise from 1 Hz to 100 Hz	3.26 pArms
Dynamic range	48 dB

4. Conclusion

This paper proposes a low voltage, low power, fast settling switched capacitor PTAT current reference circuit. Settling time is reduced with the aid of a startup circuit. The PTAT circuit exhibits good PTAT characteristics in the temperatures ranging from 10^◦C to 80^◦C while operating under a very low power. The circuit is less susceptible to power supply fluctuations and can work at supply voltages as low as 0.4 V. To test the PTAT source, a low power log- domain low frequency filter is also designed and biased with PTAT reference. Simulation results imply that the filter cutoff frequency remains unchanged irrespective of temperature variations and this validates the theory explained in the paper.

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