1. Introduction

III-V compound semiconductors have already been widely investigated as an alternative material to Silicon for future Metal -Oxide-Semiconductor Field Effect Transistors (MOS-FETs). MOS devices based on III-V compound semiconductor materials like InGaAs, with excellent performance, have been demonstrated on both 2-inch InP substrates and on a 300mm Si platform [1-5]. But, in order to become a commercially viable alternative to existing Si technologies, two major issues are yet to be solved: 1) the defective interface between III-V materials and the high-k oxide layers, and 2) the high density of defects in the most commonly investigated high-k oxides, Al₂O₃ and HfO₂.

Both of these issues have been shown to affect almost every aspect of device performance, such as the capacitance [6-11], reliability of III-V based devices [11-14], on-state electrical parameters like mobility [15], and trans-conductance [16, 17]. As a result, it becomes extremely important to reduce their impact in order to make commercial III-V MOSFET technology a reality. In this regard, the use of a new IL layer in combination with an Al₂O₃/HfO₂ or just HfO₂ stack was reported, showing improved performance and a significant reduction of the oxide traps. However, with the requirement of a thin Al₂O₃ layer for gate stack thermal stability and due to the wide defect distribution in Al₂O₃, the total density of charging oxide traps was still higher than the target (10 years reliability target: flat-band voltage shift, ΔV_fb < 30 mV at 125°C. Assuming a typical time power law exponent of 0.13, the failure criterion projects effective density of charged defects, ΔN_eff to < 3×10¹⁰/cm² at operating field, for an Effective Oxide Thickness (EOT) of 1 nm [18, 19]).

This paper is an extension of the work presented in IEEE Symposium on VLSI Technology 2017. In this paper, we demonstrate and comprehensively discuss on the process of replacing Al₂O₃ in the IL/Al₂O₃/HfO₂ gate stack with LaSiO_x. Furthermore, we elaborate on the improvements, thereof, in the interface properties and reliability for operation at V_DD=0.8 V, which exceeds the operating target for future technology nodes without any loss in the electrical performance of the MOSFET device reported earlier.

2. Experimental details

Capacitors were made starting from an MBE grown 300 nm n-type In_0.53Ga_0.47As on 2-inch n-type InP substrates. The targeted Si doping in the In_0.53Ga_0.47As grown layer was ~1×10¹⁷ at/cm³. Prior to the gate stack deposition, the substrates were cleaned in a 2M HCl solution for 5 min at room temperature and subsequently rinsed in de-ionized water. H₂S pretreatment and deposition of the IL (Inter Layer), LaSiO_x, Al₂O₃ and HfO₂ were done in an ASM Pulsar® 3000 ALD reactor. The H₂S pretreatment is done in-situ prior to the high-κ deposition. The IL used here is an ALD based layer with a κ-value ~6. The H₂S treatment and IL film deposition are both done at 250°C. Al₂O₃ and HfO₂ were deposited by ALD TMA/H₂O and HfCl₄/H₂O at 300°C. LaSiO_x is deposited by an ALD process at 250°C using the following precursors: LoLaPrime® (AIR Liquide), SiCl₄, H₂O. A 42% La concentration in the LaSiO_x is obtained by using a La:Si pulse ratio of 1:5. A full ALD cycle consists of : [[SiCl₄/purge/H2O/purge] x 5 + [LolaPrime/purge/H₂O/purge] x 1] x n. Under these conditions, a GPC of 0.1754 nm is achieved.

Dot capacitors were fabricated by sputtering 80 nm TiN using physical vapor deposition (PVD). A dry-etch process was used to etch the metal gate. An anneal in forming gas (10% H₂/N₂) was done prior to metal deposition (PDA) or post metal deposition (PMA) at 400°C for 5 min.

Implant-free quantum-well devices were also fabricated to study the impact of these passivation schemes on the device performance and reliability. A schematic diagram of the quantum-well MOSFET is shown in Fig.1. The stack for MOSFETs consists of a 15 nm un-intentionally doped In_0.53Ga_0.47As channel layer, a 3 nm InP etch stop layer and a 50 nm n+ In_0.53Ga_0.47As (Si-doped, 1×10¹⁹ cm^-3) layer, all grown on a 2-inch semi-insulating InP substrate. Fig. 2 describes the process flow used in this work. The detailed device fabrication can be found in [20]. Prior to gate stack deposition, a digital etch (cycles of HCl and H₂O₂) was used to clean and smoothen the InGaAs channel surface. The different gate stacks that were studied are depicted in Table I.

I-V and C-V measurements were used to study the impact of the gate stack on the performance of the devices. I-V measurements were carried out using HP4156 parameter analyzer and C-V measurements were performed using a HP4284A-LCR meter. The interface defect density, D_it, is extracted using the conductance method from the parallel equivalent conductance G_p [21] at room temperature. The amount of oxide traps (ΔN_eff) are measured by C-V hysteresis measurements (forward and reverse sweep of the gate voltage) at different maximum stress voltages and the corresponding shift in flat band voltage, ΔV_fb, measured between the forward and backward trace is converted into a sheet charge (ΔN_eff (E_ox)). The flat-band voltage is the gate voltage corresponding to an inflection point in the double derivative of the normalized capacitance-voltage data at a frequency of 100 kHz [21,22]. The ΔN_eff at target field as well as the voltage acceleration

Figure. 1. Schematic representation of the MOSFET device (Dimensions are not to scale).

Figure 2. Process flow used in this work for MOSFET fabrication.

                       Table 1: Split table of III-V gate stacks

Sample ID Dielectric Ref 3 nm HfO2 A 1 nm IL/3 nm HfO2 A’ 0.5 nm IL/3 nm HfO2 B 1 nm IL/1 nm Al2O3/3 nm HfO2 B’ 1 nm IL/0.2 nm Al2O3/3 nm HfO2 C 1 nm IL/1 nm LaSiOx/3 nm HfO2 C’ 1 nm LaSiOx/3 nm HfO2

factor (γ, i.e. the slope of the log-log plot of ΔN_eff vs E_ox) is reported as a figure of merit to study the oxide trap behavior [23]. Although this method does not take into account the influence of stress temperature and stress time into account, it helps in identifying the trends between different gate stack/pretreatments. Bias temperature instability (BTI) characterization using extended Measure-Stress-Measure (eMSM) technique was used to evaluate the reliability of the MOSFET devices [23]. Finally, Time-Of-Flight Secondary Ion Mass Spectrometry (TOFSIMS) was used to study the chemistry of the stacks.

Figure 3. Measured RT CV’s of gate stacks a) ‘ref’, b) A and c) B’ described in Table I at 31 frequencies between 1kHz and 1MHz. The MOSCAP devices received a PDA at 400°C, 5’ in Forming gas.

3. Results and discussion

3.1.  The IL layer development and thermal stability

Figure 4. Electrical parameters extracted for gate stacks ‘ref’, A, A‘, B’ described in Table I. a) Midgap D_it extracted from RT CV’s. b) V_fb c) ΔN_eff extracted from RT CV hysteresis by converting the measured ΔV_fb into an effective charge sheet at the interface by: ΔN_eff=ΔV_fb*C_ox/q, and reported at charging equivalent field of 3.5 MV/cm [13].  V_start condition was taken at V_g=-1.5V. d) Field acceleration exponent, γ, i.e. the slope of the log-log plot ΔN_eff vs oxide field which is a measure of the misalignment between the channel carrier energy-i.e. InGaAs E_f– and defect levels in the high-k. Filled bars represent the data after PDA, shaded bars represent the data after PMA.

Fig. 3 shows the multi-frequency (1 kHz – 1 MHz) C-V for various samples in the split table of Table I, measured at room temperature. The reduction in the D_it bump and in frequency dispersion when inserting the IL (3-A,B’) between the InGaAs channel and the HfO₂ layer clearly shows the improvement. Fig. 4 shows the result of the extraction of various electrical parameters from the measured C-V data. The extracted mid-gap D_it drops by more than a factor of 2 when inserting the IL accompanied with a negative flat band voltage, V_fb, shift (Fig. 4a,b). An H₂S treatment prior to the HfO₂ deposition has a similar effect: it reduces the D_it and shifts the V_fb by -0.15 V. Compared to an H₂S treatment, the insertion of 1 nm of the IL layer shifts the V_fb to even more negative values and a larger reduction in D_it is observed. In addition, the IL layer reduces the ΔN_eff by 1 order of magnitude and increases the γ-value to 2.5. Although 0.5 nm of the IL layer shows similar trends, an optimum is reached when using 1nm of the IL layer. This result suggests that 1 nm of IL is needed to form a closed layer passivating the interface.  When adding a thin (0.2 nm) Al₂O₃ cap on top of the IL layer, the D_it bump and frequency dispersion increase slightly (Fig. 3-B’). One can also observe that the V_fb shifts to more positive values and this goes hand in hand with a slight increase in ΔN_eff and reduction of the γ value. From these observations, a hypothesis can be put forward. Fig. 5 depicts

Figure 5. Defect band model to explain the observed changes in the γ value and total amount of charged oxide traps at a given field. The IL passivation layer is creating a dipole shifting the misalignment between InGaAs E_f and defect levels in the high-κ. In Al₂O₃ a partial overlap between deep and shallow traps is existing [9] and an almost uniform defect band is present. Therefore, the dipole created is not as effective as compared to the situation where deep and shallow traps are well separated as is proposed for the stack with HfO₂.

a cartoon of a possible explanation. Defect band modeling [24,25] has shown that although peak defect densities in Al₂O₃ are lower, a partial overlap of the defect bands induces an almost uniform distribution of defect levels around the InGaAs conduction band edge, E_c. On the contrary, HfO₂ on InGaAs shows a minimum defect density slightly below the channel E_c (~0.2 eV below E_c), which can be exploited for improving gate stack reliability by introducing an interface dipole. The assumption is that the IL layer gives rise to such a dipole shifting the defect levels up with respect to the InGaAs E_c and shifting the minimum level into the device operating range. However, dipole engineering is not effective when a broad defect band without a clear minimum is present as is the case with Al₂O₃.

From the results shown till now, one can conclude that the 1 nm IL/3 nm HfO₂ stack shows an optimum for all electrical parameters although the D_it and N_bt levels are still above the targeted values (5 x 10¹¹ /eV.cm² and 3 x 10¹⁰ /cm² respectively). However, when applying a PMA, we observe that the 1 nm IL/3 nm HfO₂ stacks degrades slightly i.e. a D_it, ΔN_eff increase and a reduction in the gamma value is observed in combination with a positive V_fb shift (Fig. 4-shaded bars). On the contrary, the stack with the Al₂O₃ cap does not degrade when a PMA is added. This result implies that although the initial gate stack properties are degraded when adding an Al₂O₃ cap, this cap can help in stabilizing the gate stack upon a PMA.

Figure 6. RT MF-CV’s measured from dot capacitors of A) 1 nm IL/3 nm HfO₂, B) 1 nm IL/1 nm Al₂O₃/3 nm HfO₂, C) 1 nm IL/1 nm LaSiO_x/3 nm HfO₂, C’) 1 nm LaSiO_x/3 nm HfO₂. Frequencies between 1 kHz-1 MHz (red-blue) were measured with logarithmic spacing. All capacitors received a PMA in forming gas for 5 minutes.

      In conclusion, the IL approach provides an improved interface quality and increases the misalignment between the InGaAs channel E_f and the defect bands in the high-κ. The improved interface quality was proven to increase the performance of InGaAs MOS devices on both planar as well as nanowire architectures. However, the introduction of a cap layer is needed to provide a good thermal stability. Although Al₂O₃ can provide a higher stability for thermal processing, the unfavorable defect band distribution in the Al₂O₃ does not allow for dipole engineering. In the next part, we show that a LaSiO_x cap can provide both an improved thermal stability and a more favorable defect band distribution.

3.2.  Replacement of Al₂O₃ stabilization cap by LaSiO_x

      Fig. 6 shows the multi-frequency C-V for various gate stacks in Table I and demonstrates the impact of the insertion of LaSiO_x between the IL passivation and HfO₂. All the dot capacitors were measured after PMA at 400^oC in forming gas anneal for 5 minutes. Although the CV’s from the 1 nm IL/3 nm HfO₂ stack (Fig. 6A) and the 1 nm IL/1 nm LaSiO_x/3 nm HfO₂ stack (Fig. 6C) look similar, one can notice that the frequency dispersion is further reduced when LaSiO_x is inserted between the IL and HfO₂. As was discussed in the previous section, an Al₂O₃ cap degrades the gate stack properties slightly. Although the difference between the stacks with the IL are subtle, a large difference can be observed when the IL is removed (Fig. 6C’). These results imply that both the IL and the LaSiO_x cap are needed to optimize the gate stack properties.

      The D_it, extracted at mid gap, and capacitance equivalent thickness (CET) are shown in fig. 7. The insertion of the IL (A) reduces the mid gap D_it as was already reported in the previous section. The replacement of Al₂O₃ (B) by LaSiO_x (C) further reduces the D_it and a reduction of the CET is also observed (CET=1.55 nm, EOT=1.15 nm). In addition, the total density of charging oxide traps drops to a value close to 1 x 10¹⁰ /cm² at E_ox

Figure 7: Mid gap D_it (bars) and CET (dots) extracted from the C-V data presented in fig. 6. Replacement of Al₂O₃ (B) by LaSiO_x (C) reduces the D_it to less than 4 x 10¹¹ /cm²eV. The CET drops to 1.55 nm.

Figure 8: ΔN_eff (bars, left axis) extracted from C-V hysteresis (V_start=V_fb – 0.5 V) by converting the measured ΔV_fb into an effective charge sheet at the interface by: ΔN_eff=ΔV_fb*C_ox/q, and reported at charging equivalent field of 3.5 MV/cm [6]. Field acceleration exponent, γ, (dots, right axis) i.e. the slope of the log-log plot ΔN_eff vs oxide field which is a measure of the misalignment between channel carrier energy-i.e. InGaAs E_f and defect levels in the high-k [18].

= 3.5 MV/cm (Fig. 8) meeting the target for 10 years operation (10 years reliability criterion: ΔV_fb < 30 mV at 125°C. Assuming a typical time power law exponent of 0.13, the failure criterion projects ΔN_eff to less than 3 x 10¹⁰ /cm² at operating field, for an EOT of 1 nm). The reduction of oxide traps below the target level is the result of the combination of the IL layer and LaSiO_x cap: while the IL layer increases the field dependence of the ΔN_eff (γ ~ 3.5), which is beneficial only for low voltage operation, the LaSiO_x cap consistently reduces the density of charging defects irrespective of the operating voltage.

Figure 9. 100 kHz CV up and down traces of the 1 nm IL/1 nm LaSiO_x/3 nm HfO₂ gate stack measured at 3 different V_max. V_start was V_fb-0.5V.

Fig. 9 shows the forward and backward sweep of gate voltage for the C-V hysteresis measured at different V_max for 1 nm IL/1 nm LaSiO_x/3 nm HfO₂ stack. At low overdrive voltages, the hysteresis is negligible. Only at higher overdrive voltages, a clear hysteresis can be measured. Notice also that the starting voltage for these measurements was carefully chosen at V_fb – 0.5 V. As was reported in [25], the C-V hysteresis measurements can largely depend on the V_start condition, as is also the case for gate stack under evaluation (Fig. 10). The more negative V_start condition reflects the discharging of deep traps that can take place during OFF-state, when the device is biased deep into the depletion and is an equally important criterion to take into account. Measuring at V_start=V_fb – 0.5 V shows that oxide trap densities are within target. Starting from a more negative V_g, the oxide trap density increases and γ decreases. This observation indicates that this gate stack has a low

Figure 10: ΔN_eff as a function of applied E_ox for the stack with 1 nm IL/1 nm LaSiO_x/3 nm HfO₂ for 2 different V_start conditions. V_start=-1.5V and V_start=V_fb-0.5V. The large dependence on the V_start conditions points to the presence of deep traps i.e. located at energies below InGaAs E_f at flatband.

amount of electron traps, but a more negative V_start charges hole traps, thereby increasing the total amount of traps during the measurement and decreasing the voltage dependence.

      Therefore, BTI measurements were performed at both positive and negative stress conditions to capture the max V_ov for both stress conditions (Fig. 11). From these CV-BTI measurements, one can see that the 1 nm IL/1 nm LaSiO_x/3 nm HfO₂ stack meets the

Figure 11: Max V_ov measured from positive and negative CV-BTI on MOS capacitors. For a target V_DD=0.8V, the max pos V_ov target (full line) is 0.53V and the max neg V_ov target (dashed line) is -0.26V (i.e. 1/3*V_DD).

Figure 12. TOFSIMS positive ion profiles from MOSCAPs of stacks a) A, b) B and c) C from Table I. All layers are aligned at the peak of the IL atom profile. max V_ov target (for a V_DD=0.8 V) for both stress conditions. When removing the IL layer, none of the targets are met. As III-V materials will be introduced in technologies operating at V_DD=0.5V and resulting target V_ov=0.33 V (=2/3*V_DD), this implies that these MOSCAP In_0.53Ga_0.47As devices with the 1 nm IL/1 nm LaSiO_x/3 nm HfO₂ gate stack surpass the IIIV reliability requirements.

      Stabilization of the IL by the Al₂O₃ or LaSiO_x cap is confirmed from the TOFSIMS profiles measured on dot capacitors that received a PMA (Fig. 12). These profiles show the mixing of the Al atoms (from the Al₂O₃) or La atoms (from the LaSiO_x) with the IL. Diffusion of the IL atoms down into the InGaAs substrate is clearly present if no cap layer is deposited between IL and the HfO₂ (Fig. 12a). When an Al₂O₃ or LaSiO_x cap is added on top of the IL (Figs. 12b and 12c) , a steep slope of the IL elements down into the substrate is observed. The hypothesis is that the mixing of the Al or La atoms with the IL atoms is increasing the stability of the IL. Although the chemistry from both Al₂O₃ and LaSiO_x cap layers can provide stabilization of the interaction of the IL with the substrate, the electrical characteristics of the LaSiO_x cap are more favorable.

      Modeling of the shallow and deep defect bands using the approach as described in [26], was done and explains the effect of the LaSiO_x cap (Fig. 13). The introduction of the IL layer narrows the distribution of the shallow defect band as well as shifts the mean energy of that band to shallower energies. Adding LaSiO_x in between the IL and HfO₂ further reduces the charging defect density. This reduction can be attributed to the stabilization that is provided by the LaSiO_x cap.

3.3.  MOSFET device characteristics

      Figs. 14 and 15 show the I_ds-V_gs and g_m-V_gs curves of the devices fabricated with stacks B (Al₂O₃ cap) and C (LaSiO_x cap). Excellent device characteristics in the form of high I_on/I_off ratio (> 2×10⁶, > 8×10⁵ at V_ds=0.05 V and 0.5 V respectively) and low SS_lin (< 75 mV/dec) were extracted for both the gate stacks. The device characteristics for stacks B, C, C’, and C’’ are given in Fig. 16 and 17. The on-state current increases (Fig. 16a and b) and the SS_lin decreases (Fig. 17) when Al₂O₃ (B) is replaced by LaSiO_x (C) between the IL layer and HfO₂. When scaling the HfO₂ to 2 nm (C’’), a CET of 1.46 nm (EOT of 1.06 nm) is achieved with a

Figure 13: Defect density profile obtained by modeling the ΔV_th vs V_gate as described in [25]. Insertion of the IL layer causes narrowing of the shallow defect band, thus enhancing γ and shifting the mean defect level of this band to shallower energy [19] but increases the density of defects at deeper energies. Insertion of LaSiO_x consistently reduces the total defect density (both shallow and deep energies). further improvement in the on-characteristics, and with a reduction in the SS_lin to 68 mV/dec. Note that the stack without the IL layer  (1 nm LaSiO_x/3 nm HfO₂ stack only, C’), exhibits high on-current compared to the stack with the 1 nm IL/1 nm Al₂O₃/3 nm HfO₂ but

Figure 14: I_ds-V_gs for L_g=10 µm, W=100 µm device.

Figure 15: G_m-V_gs for L_g=10µm, W=100µm device.

Figure 16: I_on extracted at V_t+0.5V and for V_ds=0.05V (a) and V_ds=0.5V (b), W of the devices = 100µm, Lg=10µm. Replacement of Al₂O₃ (B) by LaSiO_x (C) in the gate stack improves I_on. Further improvement can be seen when the gate stack is scaled down (C’’).

also a high SS_lin reflecting a higher mid gap D_it extracted from the MOS capacitor C-V’s (Fig. 7 and 8). Only slight changes in V_{th_lin} (~50 mV) are observed when changing the stabilization cap (Fig. 18).

      The mobility data (Fig. 19) reveal that while the dominant

Fig. 17 SS_lin for various gate stacks. Lg=50 µm. SS_lin reduces by replacing Al₂O₃ (B) with LaSiO_x (C) in the gate stack. Scaling the HfO₂ (C’’) thickness leads to further reduction.

Figure 18 V_{t, lin} for various gate stacks. L_g=50 µm. Slight Vt_lin reduction by replacing Al₂O₃ (B) with LaSiO_x (C) in the gate stack is observed.

impact of insertion of the IL layer is on the peak mobility (µ_eff at peak = 3531 cm²/V.s), the replacement of the Al₂O₃ by LaSiO_x increases the electron mobility at high charge carrier density.

Figure 19 Improvement in the mobility at low N_s (due to the introduction of IL) and high N_s (as a result of replacement of Al₂O₃ with LaSiO_x). Mobility was extracted from L_g=50 µm devices.

This observation suggests a reduction in the roughness using LaSiO_x in the gate stack instead of Al₂O₃. In addition, BTI measurements on MOSFETs confirm the good reliability observed on simple MOS capacitor structures. ΔN_eff and γ values were extracted under both positive and negative stress conditions (Fig. 20).  Under both stress conditions, we can observe a reduction of ΔN_eff when adding the IL layer and further reduction is achieved by insertion of the LaSiO_x cap. In parallel, the value of γ increases when adding the IL layer but levels off when inserting the LaSiO_x. This confirms both the

Figure 20 ΔN_eff and γ extracted from BTI measurements on MOSFETs applying both positive and negative stress conditions. The data from MOSFETs confirm the trends observed on MOSCAPs.

observation in measurement data and modeling results from the MOSCAP data i.e. the IL layer provides the misalignment between the defect levels in the high-κ and the InGaAs E_f while the LaSiO_x reduced the total charging oxide defects. At negative stress conditions, the differences are less pronounced.

      The extrapolated max V_ov and V_un at 10 years are shown in Fig. 21. Benchmarking the max V_ov of the newly proposed gate stack against Si gate stacks (Fig. 22) shows that by using the optimized gate stack III-V devices can meet even the more stringent reliability targets used for a scaled Si technology.

Figure 21. Max V_ov and V_un from BTI measurements on MOSFETs with different gate stacks.

Figure 22. Max. operating overdrive voltage as a function of CET for various gate stacks on Si (p- and n-MOS) and InGaAs. The devices with the IL/LaSiO_x/HfO₂ gate stack surpass the relability target for III-V semiconductor based technology.

4. Conclusions

We have shown in this work the improved interface and reliability properties of the IL layer. A D_it and ΔN_eff reduction are accompanied with a negative V_fb shift and an increase in the value of γ. This suggests the formation of an interface dipole. When a favorable defect band distribution is present as is the case for HfO₂, dipole engineering can be applied to misalign the defect band with the InGaAs channel E_f. However, the thermal stability of this stack is limited and a severe intermixing of the IL layer with the InGaAs substrate at typical thermal budget of a IIIV gate stack, degrades the initial improvement seen from the IL layer.

A cap is needed to stabilize this interaction and both Al₂O₃ and LaSiO_x can act as a stabilization layer by La or Al mixing with the IL-layer atoms. While the physical properties are very similar, the electrical properties in terms of oxide traps are very different. The different behavior can be explained by the presence of a broad defect band in Al₂O₃ making this cap layer not suitable for dipole engineering. On the other hand, LaSiO_x shows a more favorable defect band distribution and a further reduction of the oxide defects is observed. In addition, the interface properties are improved and low CET (~1.5 nm) was maintained.

Excellent device characteristics were demonstrated combining the IL passivation layer with the bi-layer stack consisting of 1 nm LaSiO_x/3 nm HfO₂. III-V devices with record mobility and record reliability performance at scaled EOT were demonstrated. In addition, we show that this stack can be further scaled down to 1nm EOT without loss of performance or reliability.

Conflict of Interest

The authors declare no conflict of interest.

1. S. Sioncke, J. Franco, A. Vais, V. Putcha, L. Nyns, A. Sibaja-Hernandez, R. Rooyackers, S. Calderon Ardila, V. Spampinato, A. Franquet, J.W. Maes, Q.Xie, M.Givens, F. Tang, X. Jiang, M. Heyns, D. Linten, J. Mitard, A. Thean, D. Mocuta and N. Collaert, “First demonstration of ~3500 cm2/V-s electron mobility and sufficient BTI reliability (max Vov up to 0.6 V) In0.53Ga0.47As nFET using an IL/LaSiOx/HfO2 gate stack”, in IEEE Symposium on VLSI Technology 2017, pp. T38-T39, 2017. https://doi.org/10.23919/VLSIT.2017.7998192
2.  A. Vais, A. Alian, L. Nyns, J. Franco, S. Sioncke, V. Putcha H. Yu, Y. Mols, R. Rooyackers, D. Lin, J.W. Maes, Q. Xie, M. Givens, F. Tang, X. Jiang, A. Mocuta, N. Collaert, K. De Meyer, A. Thean, “Record mobility (µeff~ 3100 cm2/Vs) and reliability performance (Vov~ 0.5 V for 10yr operation) of In0.53Ga0. 47As MOS devices using improved surface preparation and a novel interfacial layer” in IEEE Symposium on VLSI Technology, pp. 140-141. 2016. https://doi.org/10.1109/VLSIT.2016.7573410
3. C. B. Zota, F. Lindelöw, L.-E. Wernersson, and E. Lind. “InGaAs nanowire MOSFETs with ION= 555 µA/µm at IOFF= 100 nA/µm and VDD= 0.5 V” in IEEE Symposium on VLSI Technology, pp. 1-2. IEEE, 2016. https://doi.org/10.1109/VLSIT.2016.7573418
4.  N. Waldron, S. Sioncke, J. Franco, L. Nyns, A. Vais, X. Zhou, H. C. Lin, G. Boccardi, J. W. Maes, Q. Xie and M. Givens, F. Tang , X. Jiang , E. Chiu, A. Opdebeeck, C. Merckling, F. Sebaai, D. van Dorp, L. Teugels, A. Sibaja Hernandez, K. De Meyer, K. Barla, N. Collaert, A. Thean, “Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200 μS/μm at 50 nm Lg using a replacement Fin RMG flow” in IEEE International Electron Devices Meeting (IEDM), pp. 31-1. IEEE, 2015. https://doi.org/10.1109/IEDM.2015.7409805
5.  R. Suzuki, N. Taoka, M. Yokoyama, S. Lee, S. H. Kim, T. Hoshii, T. Yasuda, W. Jevasuwan, T. Maeda, O. Ichikawa, N. Fukuhara, M. Hata, M. Takenaka, and S. Takagi, “ 1-nm-capacitance-equivalent-thickness HfO2/Al2O3/InGaAs metal-oxide-semiconductor structure with low interface trap density and low gate leakage current density,” Appl. Phys. Lett. 100(13), 132906-1–132906-3 (2012). https://doi.org/10.1063/1.3698095.
6.  F Palumbo, M Eizenberg, “Degradation characteristics of metal/Al2O3/n-InGaAs capacitors”, Journal of Applied Physics, 115 (1), 014106 (2014). DOI: https://doi.org/10.1063/1.4861033
7.  G. Jiao, C. Yao, Y. Xuan, D. Huang, P.D. Ye, and M.-F. Li, “Experimental Investigation of Border Trap Generation in InGaAs nMOSFETs With Al2O3 Gate Dielectric Under PBTI Stress”, IEEE Trans. Electron Dev., 59, pp. 1661-67 (2012). https://doi.org/10.1109/TED.2012.2190417
8.  I Krylov, B Pokroy, M Eizenberg, and D Ritter, “A comparison between HfO2/Al2O3 nano-laminates and ternary HfxAlyO compound as the dielectric material in InGaAs based metal-oxide-semiconductor (MOS) capacitors”, Journal of Applied Physics, 120 (12), 124505 (2016). https://doi.org/10.1063/1.4962855
9.  K. Tang, R. Droopad, and P. C. McIntyre. “Border Trap Density in Al2O3/InGaAs MOS: Dependence on Hydrogen Passivation and Bias Temperature Stress”, ECS Trans., 69 (5), pp. 53-60 (2015). https://doi.org/ 10.1149/06905.0053ecst
10.  C. L. Hinkle, M. Milojevic, B. Brennan, A. M. Sonnet, F. S. Aguirre-Tostado, G. J. Hughes, E. M. Vogel, R. M. Wallace, “Detection of Ga suboxides and their impact on III-V passivation and Fermi-level pinning”, Appl. Phys. Lett. 94, 162101 (2009). https://doi.org/10.1063/1.3120546
11.  D. Lin, A. Alian, S. Gupta, B. Yang, E. Bury, S. Sioncke, R. Degraeve, M. L. Toledano, R. Krom, P. Favia, H. Bender, M. Caymax, K. C. Saraswat, N. Collaert, A. Thean, ”Beyond interface: The impact of oxide border traps on InGaAs and Ge n-MOSFETs”, in Proceedings of IEEE International Electron Device Meeting Technical Digest, 28.3.1 (2012). https://doi.org/10.1109/IEDM.2012.6479121
12.  S. Deora, G. Bersuker, W.-Y. Loh, D. Veksler, K. Matthews, T. W. Kim, R. T. P. Lee, R. J. W. Hill, D.-H. Kim, W.-E. Wang, C. Hobbs, P. D. Kirsch, “Positive Bias Instability and Recovery in InGaAs Channel nMOSFETs”, IEEE Transactions on Device and Materials Reliability, 13(4), 507 (2013). https://doi.org/10.1109/TDMR.2013.2284376
13.  J. Franco A. Alian, B. Kaczer, D. Lin, T. Ivanov, A. Pourghaderi, K. Martens, Y. Mols, D. Zhou, N. Waldron, S. Sioncke, T. Kauerauf, N. Collaert, A. Thean, M. Heyns, and G. Groeseneken, “Suitability of high-k gate oxides for III-V devices: a PBTI study in In0.53Ga0.47As devices with Al2O3”, in Proceedings of IEEE International Reliability Physics Symposium Technical Digest, 6A.2.1 (2014). https://doi.org/ 10.1109/IRPS.2014.6861098
14.  N. Conrad, M. Si, S. H. Shin, J. J. Gu, J. Zhang, M. A. Alam, P. D. Ye, “Low-frequency noise and RTN on near-ballistic III–V GAA nanowire MOSFETs”, in Proceedings of IEEE International Electron Devices Meeting, 20.1.1 (2014). https://doi.org/10.1109/IEDM.2014.7047086
15.  N. Taoka, M. Yokoyama, S. H. Kim, R. Suzuki, S. Lee, R. Iida, T. Hoshii, W. Jevasuwan, T. Maeda, T. Yasuda, O. Ichikawa, N. Fukuhara, M. Hata, M.Takenaka and S. Takagi, “Impact of Fermi Level Pinning Due to Interface Traps Inside the Conduction Band on the Inversion-Layer Mobility in InGaAs Metal–Oxide–Semiconductor Field Effect Transistors”. IEEE Trans. Dev. Mat. Rel. 13, 456 (2013). https://doi.org/10.1109/TDMR.2013.2289330.
16.  S. Stemmer, V. Chobpattana, and S. Rajan, “Frequency dispersion in III-V metal-oxide-semiconductor capacitors”, Appl. Phys. Lett. 100, 233510 (2012). https://doi.org/10.1063/1.4724330.
17.  S. . Johansson, M. Berg, K. M. Persson and E. Lind, “Transconductance method for characterization of border traps”, IEEE Trans. Electron Devices, vol. 60, no. 2, February 2013. https://doi.org/ 10.1109/TED.2012.2231867
18.  J. Franco, B. Kaczer, Ph. J. Roussel, J. Mitard, S. Sioncke, L. Witters, H. Mertens, T. Grasser, and G. Groeseneken, “Understanding the suppressed charge trapping in relaxed-and strained-Ge/SiO2/HfO2 p-MOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks” in Proceedings of IEEE International Electron Devices Meeting, 15.2.1 (2013). https://doi.org/ 10.1109/IEDM.2013.6724634
19.  J. Franco, A. Vais, S. Sioncke, V. Putcha, B. Kaczer, B-S. Shie, X. Shi, R. Mahlouji, L. Nyns, D. Zhou, and N. Waldron, “Demonstration of an InGaAs gate stack with sufficient PBTI reliability by thermal budget optimization, nitridation, high-k material choice, and interface dipole” in 2016 IEEE Symposium on VLSI Technology, , pp. 1-2., 2016. https://doi.org/ 10.1109/VLSIT.2016.7573371
20.  A. Alian, M. A. Pourghaderi, Y. Mols, M. Cantoro, T. Ivanov, N. Collaert, and A. Thean, “Impact of the channel thickness on the performance of ultrathin InGaAs channel MOSFET devices”, in Proceedings of IEEE International Electron Device Meeting, pp.16.6.1-16.6.4, 2013. https://doi.org/ 10.1109/IEDM.2013.6724644
21.  E. H. Nicolian and J. R. Brews, MOS Phys. and Tech., p. 215-216, Wiley Interscience, New York (2003).
22.  R. Winter, J. Ahn, P. C. McIntyre, and M. Eizenberg, “New method for determining flat-band voltage in high mobility semiconductors”, Journal of Vacuum Science & Technology B 31, 030604 (2013). https://doi.org/ 10.1116/1.4802478
23.  D. K. Schroder, Semiconductor material and device characterization. John Wiley and Sons, 2006, ISBN: 978-0-471-73906-7.
24.  B. Kaczer, T. Grasser, P.J. Roussel, J. Martin-Martinez, R. O’Connor, B. O’Sullivan, and G. Groeseneken, “Ubiquitous relaxation in BTI stressing—New evaluation and insights” in proceedings of IEEE International Reliability Physics Symposium, 2008, pp. 20-27, 2008. https://doi.org/ 10.1109/RELPHY.2008.4558858
25.  A. Vais, J. Franco, H.-C. Lin, N. Collaert, A. Mocuta, K. De Meyer, and A. Thean, “Impact of starting measurement voltage relative to flat-band voltage position on the capacitance-voltage hysteresis and on the defect characterization of InGaAs/high-k metal-oxide-semiconductor stacks”, Appl. Phys. Lett. 107, 223504 (2015). https://doi.org/ 10.1063/1.4936991
26.  V. Putcha, J. Franco, A. Vais, B. Kaczer, S. Sioncke, D. Linten and G. Groeseneken, “Impact of slow and fast oxide traps on In0.53-Ga0.47As device operation studied using CET maps”, in proceedings of IEEE International Reliability Physics Symposium 2017, XT-8.1 (2017). https://doi.org/ 10.1109/IRPS.2018.8353603

(Click Here)

(Click Here)