A New Wire Optimization Approach for Power Reduction in Advanced Technology Nodes

In advanced technologies nodes, starting from 28 nm to 7 nm and below, the power consumed of integrated circuits (ICs) becomes a big concern. Consequently, actual electronic design automation (EDA) tools are facing many challenges to have low power, reduced area and keep having required performance. To reach required success criteria, and because each picosecond and each picowatt counts, continuous development of new optimization technics is necessary. In this paper, we put to the experiment and analysis a new technic to reduce IC consumed power by optimizing its interconnections (nets). We propose an optimal algorithm and enhance it for a better compromise between having less consumed power and keep having a good design rout-ability. The new wire optimization technic based on an optimal choice of target nets for optimization: which is the list of nets consuming more than 80% of the total power in the interconnection without exceeding 30% of the total number of nets. Experiments on 14 test cases show an average total power saving of 5% on both dynamic and total power.


Introduction
Modern system on chip (SoC) and network on chip (NoC) circuits are known by the integration of complex interconnect IP which brings more difficulties for the timing closure especially with the 16 nm technology node (and below) [1]. In parallel with the circuit performance, new technology nodes allowed a very high transistors' integration to have more functionalities inside smaller die area [2], which brings many manufacturing challenges before having production circuits. On the other hand, modern designs are power-constrained (e.g., IoT, Automotive, Mobile) [3,4]. Thus, electronic design automation (EDA) tools should have all necessary functionalities for a good compromise between required circuit performances, manufacturing, and power consumption.
In advanced technology nodes, wire capacitance has become a key challenge to design closure, and this problem only worsens with each successive manufacturing process mainly due to the minimum spacing between adjacent wires [5,6]. Today, a physical implementation flow for the digital circuit should be able to play with multiple scenarios during routing to find the best compromise between timing, power, and rout-ability. [7] Details the importance of interconnect optimization and how its optimization is playing a pillar role in chip performance. Also, [8,9] Present more routing closure challenges.
Related to the power optimization, at the physical implementation, many technics are used targeting both leakage and dynamic power. [10,11] Gives some technics to reduce power on the cells' element. [12,13] present new technics for power optimization on the design network. [14,15] focus more on the technology ways to decrease total consumed power in the design.
This work introduces a new technique for power optimization during the physical implementation of an IC by optimizing the wire capacitance of its power critical interconnections (nets). We then propose a new solution that directly improves upon the original solution [16] construction by proposing an enhancement of the procedure that gets target nets for optimization. The new solution helps for having good route congestion overflow while ASTESJ ISSN: 2415-6698 keeping the same power reduction gain. The solution approach achieves improvement for both objectives, having a maximum power gain by simple nets re-routing, and reduce the overflow for better design rout-ability.
Experimental results on 14 test-cases made with most advanced technologies nodes (28, 20, 16&7 nm) demonstrate that this technique achieves an additional average of 5% on total power by targeting nets consuming more than 80% of the power. This paper makes the following contributions: • Starting with the final result from paper [16], in this paper, we propose an enhanced procedure that gets fewer data nets as a target for optimization.

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The enhanced solution helps on having acceptable routing congestion for better routing capability and, at the same time, keep having the same good power reduction gain of 5% in the average.

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Proves the benefit of this transform on power reduction on data nets by experimenting with the new flow on 14 real designs made with the most advanced technology nodes 28, 20, 16 and 7 nm.
The remainder of this paper is organized as follows. Section 2 presents the power trend on a modern integrated circuit and briefly, review the results achieved in paper [16]. Section 3 presents the enhanced solution that gets fewer targets for better routing congestion overflow as a wire promotion power-aware method. Section 4 reports our experimental results, and Section 5 concludes the paper.

Power calculation and the trend in advanced technology nodes
Equations (1), (2) and (3) summaries how the IC power can be calculated: [17][18][19] = + ℎ (1) Where: and are rise and fall energy; toggle_rate is number of toggles per time-unit; is total wire capacitance; V is the power supply voltage During IC physical implementation, only a few parameters could be optimized; for example: reduce the wire capacitance by making the interconnection wire-length shorter or by spreading. Swap cells with high internal or leakage power with lower cells' power.
In advanced nodes 28 nm and below, static power consumption represents less than 10%, on average, of the total power consumed by an IC. The dynamic circuit power is composed of the internal power that represents 20% to 30% and the switching power representing 70% to 80% of the overall consumption of a circuit [20,21]. These numbers are proved in test-cases we are using for this paper: Table 1, shows a summary of their main characteristics. Figure 1, shows their average static and dynamic power repartition. Figure 2 shows the different average power components repartition. It is evident to see that by targeting all the "Data nets", we are targeting more than 50% of the total power for optimization.

Wire optimization to reduce Net power
In our previous research [16], we presented a wire optimization technique for power saving on the interconnection at the physical implementation phase of an IC. At this stage, the circuit voltage and the TR are fixed by the circuit function, and we can't do anything to reduce them. The remaining parameter is the Internal 28% Switching 70% Leakage 2% interconnection capacitance. This represents an opportunity for significant power saving using routing transforms. The complexity of capacitance variations makes it nearly impossible for the human mind to determine which combination of layers and via structures to use for a given net in order to obtain the less possible power consumption and keeping an acceptable timing and good routing. This can be achieved through layer promotion of power critical nets, coupled with a carefully set of double-spacing non-default rules (NDRs). Enabling the routing engines to efficiently trade-off timing quality of results (QoRs) and congestion.
We have used Mentor Graphics Nitro-SoC™ [22] tool and the correspondent place and route full flow [23,24] to implement testcases used during this study.
As a review of results achieved in our previous work, reference [16] proves the following results: • 40% of data nets are consuming 92.6% of the total power as shown in Figure 3. • Start having a signifying power reduction up to 20% on power consumed by data nets when the number of target nets exceeds 40% of the total number of data nets: Figure  4. • Total power reduction percentage approaching 7 %: Figure 5. • A good compromise between the power saving and the timing/congestion was achieved by taking the cases 40% and 30% of total data nets number as a target for power optimization.

Algorithm enhancement for better congestion overflow
In the previous section, we have introduced our research by presenting a reminder of results achieved in previous work [16]. Experiment on one test-case shows an important total power saving gain exceeding 5% by targeting 30% of data nets for optimization. In this section, we will apply this optimal solution to multiple designs made with different technologies nodes. The goal is to see if this solution is robust enough for production usage. For a good comparison, we are applying the wire optimization for power reduction on an optimized post-clock-tree-synthesis (post_CTS) database (db). The baseline run that produces initial post-CTS db is a full place and route flow power-driven [23,24]. Thus, with our solution, we will be able to see the exact power gain after using existing power optimization transforms. Experiments are done on 14 test cases made with advanced technologies nodes 28 nm, 20 nm, 16

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The section below describes the main procedure that gets target nets for optimization. Its objective is to get 30% of data nets having high dynamic power.

Return first 30% of data_nets
For all trials, the target nets are 30% of data nets that have the highest power consumption, while in some test cases we see that by targeting only 20% of data nets we are targeting more than 80% of the total power consumed in the interconnection. This remark conducts us to an optimal solution by targeting a dynamic list of nets consuming more than 80% of the total power.
The new procedure that gets target nets for optimization is described below:  Table 2, shows a comparison between cases performed by using procedure#1 and procedure#2. We notice an important "Overflow" reduction in almost all test-cases.
The high overflow reduction is happening on designs having a low activity such as "Design#1, Design#2, Design#3 and Design#4". The low overflow is coming especially from the important reduction of target nets from 30% to 2% for Design#1, 3% for Design#2, and 4% for Design#3&#4. For these test-cases the low target nets percentage is sufficient to have good power reductions achieving -17.5%, -16.3%, -7.6% and -7.5% respectively.
For other designs, Design#5 to Design#13, by targeting 20% instead of 30% of data nets, we achieve almost the same power gain lower congestion overflow. Finally, one test-case "Design#14" ends with the same target nets percentage of 30% and a power gain of -19%.

Power gain on overall designs
In the previous section, we notice an important reduction of the number of target nets considered for optimization with proc#2 compare to proc#1. Fewer target nets number with almost the same or better power gain is helping for a fast run time accompanied by a better rout-ability. All of that conduct to an optimal solution, which is to target the number of nets consuming more than 80% of the total net's power with a maximum of 30% of the total nets number. Table 3, presents the dynamic and total power gain for each design using the optimal solution. An average of 5% power reduction obtained in both dynamic and total power.

Conclusion
In this paper, we present a new wire optimization technique for power reduction during IC physical implementation phase. The main outcome is the optimal choice of target nets for optimization, which is the list of power critical nets consuming more than 80% of total power in the interconnection without exceeding the number of nets of 30% of the total nets. Experiment on 14 test-cases made with advanced technologies nodes shows an important power reduction and, at the same time, keeps having good design routability.
The technique leads to an important dynamic power improvement through a simple critical Nets re-routing. The power on all data Nets reduced up to 20% and the average total power reduction in all test-cases by 5%.